GATE CS Applied Course

GATE Previous Year Wise Questions

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GATE Previous Subject Wise Questions

Data Structures Algorithms operating systems computer organization Computer Networks DBMS Graph Theory

A certain processor uses a fully associative cache of size 16 kB, The cache block size is 16 bytes. Assume that the main memory is byte addressable and uses a 32-bit address. How many bits are required for the Tag and the Index fields respectively in the addresses generated by the processor?

24 bits and 0 bits

28 bits and 4 bits

24 bits and 4 bits

28 bits and 0 bits

computer organization GATE 2019 Cache and main memory

The chip select logic for a certain DRAM chip in a memory system design is shown below. Assume that the memory system has 16 address lines denoted by A15 to A0. What is the range of address (in hexadecimal) of the memory system that can get enabled by the chip select (CS) signal?

C800 to CFFF

CA00 to CAFF

C800 to C8FF

DA00 to DFFF

computer organization GATE 2019

GATE 2019

There are n unsorted arrays: A₁, A₂, ....,A_n. Assume that n is odd. Each of A₁, A₂, ...., A_n contains n distinct elements. There are no common elements between any two arrays. The worst-case time complexity of computing the median of the medians of A₁, A₂, ....,A_n is ________ .

Ο(n log n)

Ο(n²)

Ο(n)

Ω(n²log n)

Algorithms GATE 2019

Let G be any connection, weighted, undirected graph:

I. G has a unique minimum spanning tree if no two edges of G have the same weight.
II. G has a unique minimum spanning tree if, for every cut G, there is a unique minimum weight edge crossing the cut.

Which of the above two statements is/are TRUE?

Neither I nor II

I only

II only

Both I and II

Algorithms GATE 2019

Consider the following statements:

I. The smallest element in a max-heap is always at a leaf node.
II. The second largest element in a max-heap is always a child of the root node.
III. A max-heap can be constructed from a binary search tree in Θ(n) time.
IV. A binary search tree can be constructed from a max-heap in Θ(n) time.

Which of the above statements is/are TRUE?

II, III and IV

I, II and III

I, III and IV

I, II and IV

Algorithms GATE 2019

A certain processor deploys a single-level cache. The cache block size is 8 words and the word size is 4 bytes. The memory system uses a 60 MHz clock. To service a cache-miss, the memory controller first takes 1 cycle to accept the starting address of the block, it then takes 3 cycles to fetch all the eight words of the block, and finally transmits the words of the requested block at the rate of 1 word per cycle. The maximum bandwidth for the memory system when the program running on the processor issues a series of read operations is _________ × 10⁶ bytes/sec.
Note: This was Numerical Type question.

160

145

172

124

computer organization GATE 2019

Let T be a full binary tree with 8 leaves. (A full binary tree has every level full.) Suppose two leaves a and b of T are chosen uniformly and independently at random. The expected value of the distance between a and b in T (i.e., the number of edges in the unique path between a and b) is (rounded off to 2 decimal places) ___________ .

5.71 to 5.73

4.85 to 4.86

2.71 to 2.73

4.24 to 4.26

Data Structures GATE 2019